Direct-Digitization Neural Readouts for Fully-Integrated and High-Density Neural Recording

prototype ASIC

Xiaolin Yang and Carolina Mora Lopez


Monitoring large groups of neurons in various brain regions, including superficial and deep structures, is crucial for advancing neuroscience research on cognition, motor control, behavior, among other areas [1], [2]. Current extracellular CMOS high-density neural probes are becoming the new standard in electrophysiology, allowing for simultaneous recording with excellent spatial and temporal resolution [3]–[5]. However, there is still a demand for neural recording technologies that can access a significantly larger number of neurons, allowing for the decoding of more complex motor, sensory, and cognitive tasks. To achieve this, it is necessary to develop neural probes with much higher number of channels, which requires the design of readout circuits that meet several requirements, including: i) area- and power-efficiency, ii) low noise to capture weak neural signals, iii) capability to interface with large-impedance and high-DC-offset electrodes, and iv) tolerance to artifacts caused by movement or concurrent electrical stimulation.

To address the design requirements mentioned above, the most common neural readout architecture uses multi-channel AC-coupled amplification stages followed by a multiplexed analog-to-digital converter (ADC) [3], [4]. This approach can be further optimized to reduce the channel area, thereby increasing the channel density [5]. However, the potential for area reduction is limited due to the need for large transistors to minimize the flicker noise. In recent years, direct-digitization neural readouts have been proposed to overcome this limitation, by utilizing noise shaping and oversampling techniques [6]–[12].

In our previous work [8], we propose a DC-coupled 2nd-order ∆2-∑ ADC to achieve significant area reduction. Here, chopping modulation is implemented to improve the noise performance. A new bootstrapping scheme is introduced to nullify the impact from the parasitic capacitor of the input pair transistors, thereby achieving high input impedance (663 MΩ @ 10 Hz). Furthermore, a large dynamic range (>140 mVpp) is achieved to accommodate electrode DC offsets (EDOs) and stimulation artifacts. A 16-channel prototype ASIC was successfully demonstrated in in vitro  experiments using iCell Cardiomyocytes cells cultured on a multi-electrode array (see Fig. 1).

prototype ASIC

Fig.1. Die photo of the prototype ASIC (top left) and system architecture (top right) of the ASIC reported in [8]; in vitro experimental setup and results (bottom).

In [11], we propose a follow-up architecture, which consists of an AC-coupled 1st-order ∆2-∑ ADC to further reduce the area and power consumption of the readout channel. An AC-coupling stage is used to enable a rail-to-rail EDO tolerance. Since the input stage only needs to deal with AC signals, the dynamic range can be reduced. Therefore, only a 1st-order modulation loop is needed.  The decimation filter benefits from the relaxed loop order, resulting in lower power consumption. Additionally, a system-level optimization with an ultra-low-power reference generator was implemented to further reduce the overall power consumption. To demonstrate its performance and scalability, a 128-channel prototype was fabricated. This ASIC achieves the smallest channel area (0.0051 mm2), low power consumption per channel (12.57 µW), and rail-to-rail EDO tolerance while maintaining a competitive noise performance and input range. This prototype was also used to develop a head-stage enabling in vivo experiment with passive neural probes.

128 channel ASIC

Fig.2. Overall architecture of the 128-channel ASIC reported in [11] (top left) and die photo with area partitioning (top right); in vivo experimental results and setup including a headstage and a passive neural probe (bottom).

These two area- and power-efficient direct-digitization neural readout designs aim at increasing the channel density of existing neural-recording tools. However, in order to achieve our ultimate goal of enabling access to a significantly larger number of neurons, system-level co-optimization as well as electrode material innovation are crucial. By pursuing a multi-faceted approach that addresses both electronics and materials challenges, we can unlock new possibilities for neuroscience research and pave the way for groundbreaking advancements in this field.




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